The present invention relates generally to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device which can prevent the occurrence of a short circuit between a bit line contact plug and a storage node contact plug, thereby improving the characteristics and the reliability of a semiconductor device.
A recent design trend in semiconductor devices is increased capacity, and typically, increasing the capacity of a semiconductor device requires that a chip size be increased. However, limitations exist in increasing the size of a chip, because if the size of a chip increases, the number of chips per wafer decreases and the manufacturing yield of semiconductor devices is reduced. Recently, in order to form a number of memory cells in one wafer, efforts have been made to change a cell layout and thereby decrease the area of a cell.
As a part of these efforts, a method has been proposed, in which active regions are tilted so that a layout is changed from 8F2 to 6F2.
In the 6F2 layout, tilted active regions are defined in a semiconductor substrate. Word lines and bit lines are formed on the semiconductor substrate the active regions defined therein, in such a way as to extend in directions perpendicular to each other. The word lines are located such that two word lines pass through each active region, and the bit lines are located such that one bit line passes through each active region. In detail, the bit lines are located such that one bit line passes through a portion of the active region positioned between two word lines.
In the 6F2 layout as described above, storage node contact plugs are respectively formed in portions of each active region positioned outside the two word lines that pass therethrough, and a bit line contact plug is formed in a portion of each active region positioned between the two word lines. Therefore, in a semiconductor device having the 6F2 layout, since both the storage node contact plugs and the bit line contact plug can be located in the active region, the level of integration can be increased compared to a semiconductor device having the existing 8F2 layout.
However, in the semiconductor device having the 6F2 layout as described above, a short circuit can occur between the bit line contact plug and the storage node contact plugs because the storage node contact plugs and the bit line contact plug are located side by side, and as a result the characteristics and the reliability of the semiconductor device are diminished.